In recent years, organic transistors have attracted attention as a next-generation device to be an alternative to transistors of inorganic semiconductors such as silicon.
As for the organic transistors, the devices can be produced at a lower temperature of 200° C. or less compared with the silicon semiconductor production process. Also, the organic transistor devices can be produced in a liquid-phase process that does not need a vacuum such as a printing method including inkjet and a spin coat method by dissolving an organic compound. Therefore, the devices can be produced on a plastic substrate and are expected to be applied to flexible devices such as electronic papers and electronic tags. Furthermore, the organic transistors are advantageous in that facilitation of production steps, reduction of production costs, and enlargement of a substrate size are easy, because the devices can be produced at a low temperature and normal pressure.
Meanwhile, the organic transistors are characterized in that pentacene is used for a semiconductor layer and have better properties than those of amorphous silicon, showing a mobility of approximately 1 cm2/Vs. However, inorganic oxides such as a silicone oxide film or polymer materials such as polyimide (film thickness: approximately 100 nm to 300 nm) are generally used for their gate insulating layers, and the driving voltage is as high as 20 V to 100 V. With such a high driving voltage, damage to the organic compound and increase of electric power consumption are concerned, and therefore actual use is difficult.
Now, it is necessary to reduce the threshold voltage of the transistor in order to realize driving at a low voltage.
In a field effect transistor (FET) of a metal, metal oxide layer and semiconductor structure (so-called MOS structure), the threshold voltage Vth can be represented by Formula (1).
      [          Formula      ⁢                          ⁢      1        ]                                                                                                                                  V                    th                                                                    =                                                      V                    i                                    +                                      ϕ                    s                                                                                                                          =                                                                                                    2                        ⁢                                                  ɛ                          o                                                ⁢                                                  ɛ                          s                                                ⁢                                                  qN                          ⁡                                                      (                                                          2                              ⁢                                                              ϕ                                B                                                                                      )                                                                                                                                      C                      i                                                        +                                      2                    ⁢                                          ϕ                      B                                                                                                                                (          1          )                    wherein, Vi is a voltage to be applied to a gate insulating layer, φs is a semiconductor surface potential, ∈0 is a vacuum dielectric constant, ∈s is a relative dielectric constant of a semiconductor layer, q is an electric charge, N is a carrier concentration, φB is a difference between an intrinsic level and a Fermi level in the semiconductor layer, and Ci is a capacitance of the gate insulating layer.
Formula 1 indicates that the threshold voltage can be reduced by increasing the capacitance Ci of the gate insulating layer.
Furthermore, the capacitance of the gate insulating layer can be represented by Formula 2.
      [          Formula      ⁢                          ⁢      2        ]                                            C            i                    =                                                    ɛ                0                            ⁢                              ɛ                r                                      d                                                (          2          )                    wherein, Ci and ∈0 are as defined in Formula (1), d is a thickness of the gate insulating layer, and ∈r is a relative dielectric constant of the gate insulating layer.
That is, it is important to increase the relative dielectric constant ∈r of the gate insulating layer or to decrease the film thickness d of the gate insulating layer in order to reduce the capacitance of the gate insulating layer and realize driving at a low threshold voltage.
Examples of an attempt to increase the relative dielectric constant of the gate insulating layer include Patent Document 1. Generally, however, many of materials having a higher relative dielectric constant are inorganic oxides, and it is necessary to use a conventional silicon semiconductor process when films of such inorganic oxides are formed. Therefore, production at a low temperature and without the use of a vacuum process is difficult.
On the other hand, examples of an attempt to decrease the film thickness of the gate insulating layer include Non-Patent Documents 1 to 3. They all use a self-assembled layer of an organic molecule having a film thickness of approximately several nanometers, which is almost equal to the molecular length when the molecule is standing, allowing low voltage driving at an absolute value of the threshold voltage of 2 V or less and a driving voltage of 5 V or less. In addition, the self-assembled layer is advantageous also in that it allows production at a high temperature and without the use of a vacuum process.
Examples of another attempt to improve luminous efficiency of an organic light emitting diode using an organic molecule and extend its lifetime include Patent Document 2.    Patent Document 1: Japanese Unexamined Patent Publication No. 2003-25820    Patent document 2: Japanese Unexamined Patent Publication No. 2004-103547    Non-Patent Document 1: “Nature”, vol. 431, p.p. 963-966, 2004, Marcus Halik et al.    Non-Patent Document 2: “PNAS”, vol. 102, No. 13, p.p. 4678-4682, 2005, Myung-Han Yoon et al.    Non-Patent Document 3: “Applied Physics Letter”, vol. 85, p.p. 4400, 2004, Soeren Steudel et al.